Pipelined multi-master DDR3 SDRAM controller
- Parametric configuration (size & timing).
- Zero wait-state pipelining between different masters (back2back).
- Zero wait-state pipelining between wr2wr & rd2rd bursts (back2back if same row).
- Maskable (write) bursts.
- Automatic refresh generation.
- Power saving mode (with self refresh).
- ODT control (at memory & self).
- ZQ calibration.
- (Training sequence calibration.)
- Soft or hard PHY.
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