Reusable Intellectual Propertys for ASIC and FPGA designs
A swedish IP provider with slim-line high-speed controllers.
Our goal is to make very high speed IP-blocks with extreme low gate count.
For the time being we can offer sdram, ddr2 & ddr3 controllers and a PTP handler.
All with easy-to-use test-benches and comprehensive documentation.
Until further notice all RTL code are in Verilog only.
